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1 KiB ROM with Cache (expandable)

ROMromsROM002Archived Feb 15, 2026
โœ…Tested & Functional
Authors:LLucas
Endorsed by:mattbatwings
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A cached read only memory designed to hold CPU instructions

Input

Page swap address, Address within cache

Output

Values stored in barrels

Speed

7 tick read, 10 word/sec swap

Considerations

Notes

Page size: 32 word / 64 Byte. Main memory: 16 pages / 1 024 Byte. Main memory size: 2 blocks/bit.

Attachments

Schematic ยท SCHEM
ROM002_1KiBROM_1.schem
ROM002_1KiBROM_1.schem
  • Version: 1.21.8
  • Size: 82x32x37
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